The evolution of integrated circuit (IC) fabrication technology has made possible the fabrication of microelectronic complexes, which perform a wide variety of functions and are characterized by varying degrees of complexity. Microelectronic complexes, that is systems and groups of discrete microelectronic functional modules, implement an important range of electronic devices, including microcomputers and microprocessors, and have important application in the design of electronic systems. Examples of such microelectronic complexes include PCBs, MCMs and semiconductor wafers for Wafer-Scale Integration (WSI) applications or “silicon circuit boards”, containing a plurality of chips and/or integrated circuits.
In the case of a silicon wafer, the wafer is typically divided into a plurality of discrete functional cells. These cells are laid out within a dedicated area on the wafer surface, typically forming a grid-like array, such that a finished silicon wafer may contain from 100 to 1000 finished cells. Once packaged, the wafer may include hundreds, if not thousands, of connectors, pins and wires, among other possibilities, for external connection to a circuit board, permitting signals to be exchanged between the circuits/chips and the circuit board.
A problem commonly faced during the design and fabrication of microelectronic complexes on silicon wafers is the restricted amount of surface area available on the planar interconnect medium of the wafer, within which confines the microelectronic complex must be built. Even with the development of new fabrication technologies that permit an increased density of integrated circuits per wafer, the larger, more complex arrangements of microelectronic functional modules become infeasible for fabrication on a single wafer, which typically provides a single, two-dimensional interconnect plane.
Furthermore, as the microelectronic complexes formed on a silicon wafer become larger and we see an increased density of integrated circuits per wafer, the heat dissipation requirement per wafer increases proportionally. More specifically, the requirement for efficient and maximized heat dissipation from the wafer becomes extremely important, in order to prevent over-heating and subsequent malfunctioning or failure of, as well as possible damage to, the functional cells of the wafer.
Existing solutions to the problem of limited circuit density per silicon wafer include the mounting of chips directly onto the active surface of the silicon wafer, as well as the attachment of printed circuit boards to the silicon wafer. Although both solutions provide for increased density per wafer, this density is still limited as the circuitry continues to be restricted to the interconnect plane of the wafer.
The above-described problem extends to most microelectronic complexes formed on planar bodies, including PCBs and MCMs, among other possibilities. Unfortunately, the circuit density and the cooling capacity of a microelectronic complex are both limited when the microelectronic complex is restricted to a two-dimensional interconnect plane.
Against this background, it clearly appears that a need exists in the industry for a novel high-density architecture for a microelectronic complex on a planar body.